40Pin Header
Most boards from the UP Series include a 40pin header for Embedded I/O interfaces, such as:
- GPIO
- I2C
- UART
- SPI
- PWM
- ADC
- I2S
The Lattice LCMXO2-640HC-6MG132C act as a level shifter between the Intel Soc and the HAT interfaces.
Because almost every connection to HAT passes through the FPGA is also possible to provide customized firmware to expose other peripherals/pin mapping on HAT or to implement custom devices in the FPGA fabric.
This is the generic table that describe the 40pin header:
The 40pin functionalities are enabled with a custom DKMS driver which can be installed following the instructions on the dedicated Github Repository:
The driver has been tested with Ubuntu 20.04 and 22.04 LTS kernel 5.15, but it can be leveraged also with newer Kernels and other Linux Distributions and Yocto (see UP Board BSP as reference).
Once the driver is properly installed you can follow the examples on
How to use the peripherals on 40 Pin Header
The 40pin functionalities are enabled with a custom SDK that leverages Windows EAPI.
The driver can be installed on Windows IoT Enterprise 2021, Windows 10 and Windows 11 and you can download it from our Downloads Section including the reference applications:
