Sync dev to master #3675

jerryz123 · 2024-08-19T07:10:54Z

Related issue:

Type of change: bug report | feature request | other enhancement

Impact: no functional change | API addition (no impact on existing code) | API modification

Development Phase: proposal | implementation

Release Notes

`flow` must be explicitly passed to `Queue.irrevocable` to avoid mismatching the arguments.

* add DontCare for user/echo bits in Channel A/C/D * add DontCare for messages without any data payload

* bump flake * remove legacy firtool option

…ubsystem

Fix CSRIO bidir connection

Add DelayQueue

Co-authored-by: Sihao Liu <sihao@cs.ucla.edu>

Move rocket-related config fragments to rocket/Configs.scala

DontCare should come first before waiveAll so that matching userfield bewteen bundles can be connected Please refer to the issue page below. ucb-bar/chipyard#1888

I think this module is not tested during Chisel version is updated. I fixed compiler error by chiselTypeOf

Add IO Connections for Custom User Field in TL Channels within Xbar

Fix support for vector units with Zvfh

Support vector extensions

…load/store

B ext

Prevent bypasses from vector instructions | fix vsets

linux-foundation-easycla · 2024-08-19T07:11:06Z

✅ login: jerryz123 / name: Jerry Zhao (dc24b03, 3172ee6, 8ff7929, ea9979b, 44ad268, 80ff66a, eb141eb, 5de77a2, 8f220f1, de696aa, 91a6038, e0ea903, 5453ae9, 7960fe8, af11ed4, 9f92ac6, 31e1ed8, 521a1d1, 94d1b43, 203fc1f, b60568c, ee00619, f85496e, cc1395b, ce9a2ec, 3279f17, 3bd6174, 7a12ab9, aea0064, cd4b193, a73b797, 0c510ec, 4ac1529, 516288f, 65164f8, f745cff, 6d88d6c, 56a4da7, 043926a, d8de943, 3cec0f0, 1aa0104, 8881ccd, f43041d, 61b59e9, c82a93d, c68371e, b613fbe, c10ce93, d9a3d99, 87b3a4d, 59e86fd, c37e630, fd51b74, 2fb2c5f, ad37acb, 90da5bc, 1709858, d48b45d, ea35ee2, 04cbdf3, ef1d671, b8d59a0, 2e1bfe5, 93fe30e, 20a5fe3, 51e8773, 2453dd4, cd4b38b, b50ad58, 2371ef6, 39b2188, 0b2d940, 15c63b5, a235684, 28bf141, 286e842, 37e1d56, 51bfd75, 80dffc8, b036fa2, d92922a, ea3d882, 4996086, 0a00146, b33b8dd, 49e7d27, f3951e7, ef2876c, 10bc824, c025c2e, f51bca4, 749a3ea, 9dc08fe, 22cc8aa, ed09cea, 4bd4675, dfaa357, 93cef4e, f8105ce, f228714, 527560a, 0bff786, 5bcdcb2, 2f462f5, 5a17c56, 0e88fc0, 52b8c6e, c69faba, 724974d, 2ff60ca, 3c888a2, 6d00957, f388fb1, 072bc41, a721154, baa9f45, 0b556a1, f13a570, bf6e57d, ebef114, c60ad43, 7f8f08b, ebe730b, 01303e7, d8f6caf, db35cb8, 73ee196, fbd0fb8, 174a4b9, e81ed19, c79db98, 1e9fef1, dd26375, 1ba5acd, caa9d8a, bff48a8, e47a188, 224b91f, d8afe64, 6e554f3, 79626c0, 28bbca5, 48602b9, b7e4f05, 32b2d12, 84409c8, 0292f13, 66bd400, b47fdf9, 09bbf5c, a68cfc1, c558393, 04d4271, 51a5485, 83e8c6b, 044a434, 48037e9, b99a77c, 50559ea, ee7f6a6, 7e16264, e53bbfc, c2651f4, 1dbaf6d, 37cfd6f, 0464c21, e3da6bd, 72690b0, 49158aa, 53bf263, f50b0db, 4b33216)
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jerryz123 and others added 30 commits September 26, 2023 16:14

Remove old sbus arg to CoherentBusTopoParams

51bfd75

Support CloneCluster

0a00146

Rename Element to HierarchicalElement

8f220f1

Add set_vconfig to vector-unit

ad37acb

Propagate request size/cmd to TLB resp

bff48a8

Add SimpleHellaCacheIF mask

d8f6caf

Fix the missing flow argument in TileLink/ToAXI4 (#3505)

71a1b6f

`flow` must be explicitly passed to `Queue.irrevocable` to avoid mismatching the arguments.

Fix the missing DontCare in TileLink Edges/Delayer (#3504)

bb74155

* add DontCare for user/echo bits in Channel A/C/D * add DontCare for messages without any data payload

Bump flake dependencies (#3506)

4fed21e

* bump flake * remove legacy firtool option

Switch to SortedMap for tile node maps

516288f

Add tile_reset_domain alias to element_reset_domain in TilePRCIDomain

fd51b74

Switch to separate cluster-local bus locations

f745cff

Add documentation to DCache about datapath of meta/data arbiter (#3510)

2a190d2

Generalize WithNBigCores to support clustered cores

ef1d671

Rename trace crossing nodes to crossing nodes

e0ea903

Fix int clock crossings to use CLINT/PLIC domains

d48b45d

Fix any unassigned clocks due to removal of implicit clock from BaseS…

8881ccd

…ubsystem

Fix intsynccrossings not receiving a clock

0e88fc0

Add SimpleLazyRawModule

f85496e

Synchronize ext-ints within the ibus domain

59e86fd

Fix RoCCCSRIO bidir

b47fdf9

Merge pull request #3516 from chipsalliance/jerryz123-patch-2

c60ad43

Fix CSRIO bidir connection

Remove Chisel 3.6 support (#3515)

8907e63

Add DelayQueue variations

b2b78fd

Add docstrings

4dc6305

Merge pull request #3520 from abejgonzalez/delay-queue

04cbdf3

Add DelayQueue

Fix r_pte update condition when S2 PTE cache hit (#3525) (#3526)

5087e53

Co-authored-by: Sihao Liu <sihao@cs.ucla.edu>

add sonatype snapshots repo for test chisel releases (#3527)

180e4bc

remove torture

1101d21

move cde and hardfloat to dependencies folder

b0a3b66

jerryz123 and others added 28 commits June 29, 2024 22:01

Add pgLevels check to Tile

93cef4e

Clean up TileAttachConfig | add atTileIds method

0464c21

Merge pull request #3655 from chipsalliance/split-configs

f50b0db

Move rocket-related config fragments to rocket/Configs.scala

Add IO Connections for Custom User Field in TL Channels within Xbar

54ff555

DontCare should come first before waiveAll so that matching userfield bewteen bundles can be connected Please refer to the issue page below. ucb-bar/chipyard#1888

Fix for compilation error in PhysicallFilter

afe77ac

I think this module is not tested during Chisel version is updated. I fixed compiler error by chiselTypeOf

Merge pull request #3637 from ksungkeun84/master

4b33216

Add IO Connections for Custom User Field in TL Channels within Xbar

Properly generate zvfh isa string

286e842

Fix zvfh capitalization

e53bbfc

Fix FP16 storegen bug

04d4271

bug fix to io.out.bits.store

794c5b1

Merge pull request #3659 from chipsalliance/zvfh

306467d

Fix support for vector units with Zvfh

Support vector extensions

ee7f6a6

Merge pull request #3665 from chipsalliance/v_exts

3e20954

Support vector extensions

Add support for zba/zbb/zbs-enabled tiles

1aa0104

Revert to single global ALU

c68371e

Fix rv64uzba test names

37cfd6f

Support Zba in rocket

90da5bc

Add Zbb support

83e8c6b

Support Zbs extension

51a5485

Fix rv32b

09bbf5c

Add b-ext tests to CI

1dbaf6d

Set 'b' in isaStr if zba+zbb+zbs

7e16264

Add HugeCore config that adds Zfh/Zba/Zbb/Zbs

48037e9

Disable ma_data rv32 tests in CI, rocket does not support misaligned …

044a434

…load/store

Merge pull request #3667 from chipsalliance/b_ext

7c32936

B ext

Prevent bypasses from vector instructions

49158aa

Fix bit indices for rd when computing AVL for vsets

72690b0

Merge pull request #3670 from chipsalliance/vec_bypasses

14b81e4

Prevent bypasses from vector instructions | fix vsets

jerryz123 merged commit cff28b8 into master Aug 21, 2024
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Sync dev to master #3675

Sync dev to master #3675

jerryz123 commented Aug 19, 2024

linux-foundation-easycla bot commented Aug 19, 2024

Sync dev to master #3675

Sync dev to master #3675

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jerryz123 commented Aug 19, 2024

linux-foundation-easycla bot commented Aug 19, 2024